DSP Processor Core-Based Wireless System Design

This thesis considers the design of wireless communications systems which are implemented as highly integrated embedded systems comprised of a mixture of hardware components and software. An introductionary part presents digital communications systems, classification of processors, programmable digital signal processing (DSP) processors, and development and implementation of a flexible DSP processor architecture. This introduction is followed by a total of seven publications comprising the research work. In this thesis the following topics have been considered. Most of the presented research work is based on a customizable fixed-point DSP processor which has been implemented as a highly optimized hard core for use in typical DSP applications. The studied topics cover a plethora of aspects starting from the initial development of the processor architecture. Several real-time DSP applications, such as MPEG audio decoding and GSM speech coding, have been developed and their performance with this particular processor have been evaluated. The processor core itself as a bare hardware circuit is not usable without various software tools, function libraries, a C-compiler, and a real-time operating system. The set of development tools was gradually refined and several architectural enhancements were implemented during further development of the initial processor core. Furthermore, the modified Harvard memory architecture with one program memory bank was replaced with a parallel program memory architecture. With this architecture the processor accesses several instructions in parallel to compensate for a potentially slow read access time, a characteristic which is typical of, for example, flash memory devices. The development flow for heterogenous hardware/software systems is also studied. As a case study, a configurable hardware block performing two trigonometric transforms was embedded into a wireless LAN system described as a dataflow graph. Furthermore, implementation aspects of an emerging communications system were studied. A high-level feasibility study of a W-CDMA radio transceiver for a mobile terminal was carried out to serve as a justification for partitioning various baseband functions into application-specific hardware units and DSP software to be executed on a programmable DSP processor.